----------------------------------------------------------------------
-- Module name:     INTERCON TEST VECTORS
--
-- History:         Project complete:           OCT 03, 2001
--                                              WD Peterson
--                                              Silicore Corporation
--
-- Release:         Notice is hereby given that this document is not
--                  copyrighted, and has been placed into the public
--                  domain.  It may be freely copied and distributed
--                  by any means.
--
-- Disclaimer:      In no event shall Silicore Corporation be liable
--                  for incidental, consequential, indirect or special
--                  damages resulting from the use of this file.
--                  The user assumes all responsibility for its use.
--
----------------------------------------------------------------------

----------------------------------------------------------------------
--
--     I/O SIGNALS
-- ----------------------
-- E
-- X
-- T E EE E EEEEEEEE EEEEEEEE E   E
-- C A AA C DDDDDDDD DDDDDDDD S E G
-- L C DD Y RRRRRRRR WWWWWWWW T W N
-- K K RR C DDDDDDDD RRRRRRRR B E T                COMMENTS
----------------------------------------------------------------------
-- I O OO O OOOOOOOO OOOOOOOO O O O
----------------------------------------------------------------------

----------------------------------------------------------------------
-- System initialization (after reset).
----------------------------------------------------------------------

:  R 0 00 0 UUUUUUUU A5A5A5A0 0 0 0
:  R 0 00 0 UUUUUUUU A5A5A5A0 1 1 0


----------------------------------------------------------------------
-- MASTER #1 acquires the bus (reset was handled earlier).
----------------------------------------------------------------------

:  R 1 08 1 UUUUUUUU A5A5A5A1 1 1 1  -- Eight phases of a BLOCK WRITE cycle
:  R 1 09 1 UUUUUUUU A5A5A5A1 1 1 1
:  R 1 0A 1 UUUUUUUU A5A5A5A1 1 1 1
:  R 1 0B 1 UUUUUUUU A5A5A5A1 1 1 1
:  R 1 0C 1 UUUUUUUU A5A5A5A1 1 1 1
:  R 1 0D 1 UUUUUUUU A5A5A5A1 1 1 1
:  R 1 0E 1 UUUUUUUU A5A5A5A1 1 1 1
:  R 1 0F 1 UUUUUUUU A5A5A5A1 1 1 1
:  R 0 08 0 A5A5A5A1 A5A5A5A1 0 1 1 -- Release the bus


----------------------------------------------------------------------
-- MASTER #2 acquires the bus.
----------------------------------------------------------------------

:  R 1 10 1 UUUUUUUU A5A5A5A2 1 1 2  -- Eight phases of a BLOCK WRITE cycle
:  R 1 11 1 UUUUUUUU A5A5A5A2 1 1 2
:  R 1 12 1 UUUUUUUU A5A5A5A2 1 1 2
:  R 1 13 1 UUUUUUUU A5A5A5A2 1 1 2
:  R 1 14 1 UUUUUUUU A5A5A5A2 1 1 2
:  R 1 15 1 UUUUUUUU A5A5A5A2 1 1 2
:  R 1 16 1 UUUUUUUU A5A5A5A2 1 1 2
:  R 1 17 1 UUUUUUUU A5A5A5A2 1 1 2
:  R 0 10 0 A5A5A5A2 A5A5A5A2 0 1 2 -- Release the bus


----------------------------------------------------------------------
-- MASTER #3 acquires the bus.
----------------------------------------------------------------------

:  R 1 18 1 UUUUUUUU A5A5A5A3 1 1 3  -- SINGLE WRITE cycle
:  R 0 19 0 UUUUUUUU A5A5A5A3 0 1 3  -- Release the bus


----------------------------------------------------------------------
-- MASTER #0 acquires the bus.
----------------------------------------------------------------------

:  R 1 00 1 UUUUUUUU A5A5A5A0 1 1 0  -- Eight phases of a BLOCK WRITE cycle
:  R 1 01 1 UUUUUUUU A5A5A5A0 1 1 0
:  R 1 02 1 UUUUUUUU A5A5A5A0 1 1 0
:  R 1 03 1 UUUUUUUU A5A5A5A0 1 1 0
:  R 1 04 1 UUUUUUUU A5A5A5A0 1 1 0
:  R 1 05 1 UUUUUUUU A5A5A5A0 1 1 0
:  R 1 06 1 UUUUUUUU A5A5A5A0 1 1 0
:  R 1 07 1 UUUUUUUU A5A5A5A0 1 1 0
:  R 0 00 0 A5A5A5A0 A5A5A5A0 0 1 0 -- Release the bus


----------------------------------------------------------------------
-- MASTER #1 acquires the bus.
----------------------------------------------------------------------

:  R 1 08 1 A5A5A5A1 A5A5A5A1 1 0 1  -- Eight phases of a BLOCK READ cycle
:  R 1 09 1 A5A5A5A1 00000000 1 0 1
:  R 1 0A 1 A5A5A5A1 A5A5A5A1 1 0 1
:  R 1 0B 1 A5A5A5A1 A5A5A5A1 1 0 1
:  R 1 0C 1 A5A5A5A1 A5A5A5A1 1 0 1
:  R 1 0D 1 A5A5A5A1 A5A5A5A1 1 0 1
:  R 1 0E 1 A5A5A5A1 A5A5A5A1 1 0 1
:  R 1 0F 1 A5A5A5A1 A5A5A5A1 1 0 1
:  R 0 08 0 A5A5A5A1 A5A5A5A1 0 0 1  -- Release the bus


----------------------------------------------------------------------
-- MASTER #2 acquires the bus.
----------------------------------------------------------------------

:  R 1 10 1 A5A5A5A2 A5A5A5A2 1 0 2  -- Eight phases of a BLOCK READ cycle
:  R 1 11 1 A5A5A5A2 00000000 1 0 2
:  R 1 12 1 A5A5A5A2 A5A5A5A2 1 0 2
:  R 1 13 1 A5A5A5A2 A5A5A5A2 1 0 2
:  R 1 14 1 A5A5A5A2 A5A5A5A2 1 0 2
:  R 1 15 1 A5A5A5A2 A5A5A5A2 1 0 2
:  R 1 16 1 A5A5A5A2 A5A5A5A2 1 0 2
:  R 1 17 1 A5A5A5A2 A5A5A5A2 1 0 2
:  R 0 10 0 A5A5A5A2 A5A5A5A2 0 0 2  -- Release the bus


----------------------------------------------------------------------
-- MASTER #3 acquires the bus.
----------------------------------------------------------------------

:  R 1 19 1 UUUUUUUU A5A5A5A3 1 0 3  -- SINGLE READ cycle
:  R 0 1A 0 UUUUUUUU 00000000 0 0 3  -- Release the bus


----------------------------------------------------------------------
-- MASTER #0 acquires the bus.
----------------------------------------------------------------------

:  R 1 00 1 A5A5A5A0 A5A5A5A0 1 0 0  -- Eight phases of a BLOCK READ cycle
:  R 1 01 1 A5A5A5A0 00000000 1 0 0
:  R 1 02 1 A5A5A5A0 A5A5A5A0 1 0 0
:  R 1 03 1 A5A5A5A0 A5A5A5A0 1 0 0
:  R 1 04 1 A5A5A5A0 A5A5A5A0 1 0 0
:  R 1 05 1 A5A5A5A0 A5A5A5A0 1 0 0
:  R 1 06 1 A5A5A5A0 A5A5A5A0 1 0 0
:  R 1 07 1 A5A5A5A0 A5A5A5A0 1 0 0
:  R 0 00 0 A5A5A5A0 A5A5A5A0 0 0 0  -- Release the bus

